{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Chap_2Lesson05EmsysNew - 8051 AND ADVANCED PROCESSOR...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
2008 Chapter-2 L5: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 1 8051 AND ADVANCED PROCESSOR ARCHITECTURES Lesson-5: Hardware Interrupts of 8051
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2008 Chapter-2 L5: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 2 Interrupt Sources Interrupt Sources External INT0 interrupt T0 overflow interrupt External INT1 interrupt T1 overflow interrupt SI serial UART or Synchronous mode interrupt SI synchronous serial mode interrupt (separate in few families of 8051) Timer 2 interrupt in 8052
Background image of page 2
2008 Chapter-2 L5: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 3 SFR IE for interrupts enabling bits SFR IE for interrupts enabling bits SFR to mask (disable) or unmask (enable) the interrupts in 8051 Programming of SFR IE (Interrupt Enable) register at address 0xA8 for the byte or Programming of IE using Bit addresses 0xA8 to 0xAF for the individual bits
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon