ECE546_Spring2011_Final

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ECE 546 Final Exam (2 hours, open book/notes) May 4 th , 2011 Prof. Dev Gupta 1. 40 Marks It was required to design a VLSI that incorporated a complete modem and a linear block code based forward error correction module. The generator was to be a systematic realization of the following matrix: 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1 0 1 1 A mistake was made in the design of the encoder and all the parity bits were inverted going into the transmit circuits of the modem. For testing reasons, the decoder was built in a way where the syndrome was brought out to pins and returned back via outside connections for further processing by the decoder: a) What is the systematic generator matrix? b) What is the correct parity check matrix assuming error had not been made? c) If the data word transmitted corresponds to data bits 111, and an error 010000 occurs during transmission, what will the decoder decode to because of the design error? d) Can you design a small combinatoric circuit which can be inserted between “syndrome
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  • Fall '11
  • Zhlai
  • Forward error correction, parity check matrix, Design error, Prof. Dev Gupta, systematic generator matrix, small combinatoric circuit

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