cs61c_su13_fin_review

cs61c_su13_fin_review - CS61C Summer 2013 Final Review...

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CS61C Summer 2013 Final Review Session Albert, Jeffrey, Justin, Kevin, Sagar, Shaun Please sit as close to the front as possible; some slides contain small text
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● Time/Location: Friday, August 16th, 9am- 12pm in 155 Dwinelle ● Rules: Bring : Pencil, Eraser, TWO double-sided sheets of handwritten notes Provided : MIPS Green Sheet, exam with whitespace for work, scratch paper, time keeping '2 127 Bring : Books, printed notes, calculators ● Additional resources available on Piazza @893 Reminders
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Outline 1. VM and Cache 2. SIMD and OpenMP 3. FSMs, Boolean Logic, and Timing 4. Datapath and Control 5. Pipelining and Hazards 6. MapReduce
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VM and Cache (1/5) Machine Specs (one level of Cache and VM): 1 MiB Physical Addr. Space 4 GiB Virtual Addr. Space 4 KiB Page Size 16 KiB 8-way set assoc., write-through cache w/LRU 1 KiB cache block size 2-entry TLB, LRU a) What is the T:I:O bit breakup for the cache (assuming byte addressing)? b) What is the VPN: PO bit breakup for VM (assuming byte addressing)?
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VM and Cache (2/5) Machine Specs (one level of Cache and VM): 1 MiB Physical Addr. Space, 4 GiB Virtual Addr. Space, 4 KiB Page Size, 16 KiB 8-way set assoc., write-through cache w/LRU, 1 KiB cache block size, 2-entry TLB, LRU The following code is run on the system: #define NUM_INTS 8192 int *A = (int *)malloc(NUM_INTS * sizeof (int)); int i, total = 0; for(i = 0; i < NUM_INTS; i+=128) A[i] = i; for(i = 0; i < NUM_INTS; i+=128) total += A [i]; // SPECIAL
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VM and Cache (3/5) Machine Specs (one level of Cache and VM): 1 MiB Physical Addr. Space, 4 GiB Virtual Addr. Space, 4 KiB Page Size, 16 KiB 8-way set assoc., write-through cache w/LRU, 1 KiB cache block size, 2-entry TLB, LRU The following code is run on the system: #define NUM_INTS 8192 int *A = (int *)malloc(NUM_INTS * sizeof(int)); int i, total = 0; for(i = 0; i < NUM_INTS; i+=128) A[i] = i; for(i=0; i<NUM_INTS; i+=128) total+=A[i]; //ME c) Calculate the hit percentage for the cache
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VM and Cache (4/5) Machine Specs (one level of Cache and VM): 1 MiB Physical Addr. Space, 4 GiB Virtual Addr. Space, 4 KiB Page Size, 16 KiB 8-way set assoc., write-through cache w/LRU, 1 KiB cache block size, 2-entry TLB, LRU The following code is run on the system: #define NUM_INTS 8192 int *A = (int *)malloc(NUM_INTS * sizeof(int)); int i, total = 0; for(i = 0; i < NUM_INTS; i+=128) A[i] = i; for(i=0; i<NUM_INTS; i+=128) total+=A[i]; //ME d) Calculate the hit percentage for the TLB
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VM and Cache (5/5) Machine Specs (one level of Cache and VM): 1 MiB Physical Addr. Space, 4 GiB Virtual Addr. Space, 4 KiB Page Size, 16 KiB 8-way set assoc., write-through cache w/LRU, 1 KiB cache block size, 2-entry TLB, LRU The following code is run on the system: #define NUM_INTS 8192 int *A = (int *)malloc(NUM_INTS * sizeof(int)); int i, total = 0; for(i = 0; i < NUM_INTS; i+=128) A[i] = i; for(i=0; i<NUM_INTS; i+=128) total+=A[i]; //ME e) Calculate the hit percentage for the page table
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SIMD (1/6) Remember Polynomial Differentiation: A degree n - 1 polynomial is uniquely determined by n integer coefficients a_0 … a_(n-1), which we can represent as an array of integer values. For example, f(x) = 1 + 3x^2 can be represented by: int f[] = {1, 0, 3}; Taking the derivative of a polynomial reduces its degree by 1 (Hint: What are the implications for the length of the array into which we store the derivative?)
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cs61c_su13_fin_review - CS61C Summer 2013 Final Review...

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