Shifters mux chips wires and new control signals to

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ers, mux chips, wires, and new control signals to implement addpr. If necessary you may replace original labels. a) Make up the syntax for the I-type MAL MIPS instruction that does it (show an example if the pointer lives in $v0, and the constant is 5). On the right, show the register transfer language (RTL) description of addpr Datapath and Control (3/5) On the right is the single-cycle MIPS datapath (no pipelining). Modify the diagram using adders, shifters, mux chips, wires, and new control signals to implement addpr. If necessary you may replace original labels. b) Change as little as possible in the datapath above and list all changes. Datapath and Control (4/5) On the right is the single-cycle MIPS datapath (no pipelining). Modify the diagram using adders, shifters, mux chips, wires, and new control signals to implement addpr. If necessary you may replace original labels. c) We now want to set all the control lines appropriately. List what each signal should be, an intuitive name or {0, 1, x for don’t care}. Include any new control signals you added. RegDst, RegWr, nPC_sel, ExtOp, ALUSrc, ALUctr, MemWr, MemtoReg Datapath and Control (5/5) d) In the context of a single-cycle CPU, lw used to be the critical path instruction, since it utilized the most components of our datapath. Use the terms below to create an expression that will determine how much slower our clock period will be if we also consider the addpr instruction: PCRegClkToQ, InstMemAccess, ControlLogicDelay, RegFileAccess, ALUDelay, DataMemAccess, RegSetup, RegHold, MemSetup, MemHold Pipelining and Hazards (1/5) Consider the 5-stage single-issue pipelined MIPS datapath consisting of Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Mem, and Write-Back (WB). You are given: # $s0 to $s3 = 56, 30, 30, 7 # $t0 to $t4 = 7, 7, 7, 7, 7 add $t0, $s0, $0 and $t1, $t0, $s1 or $t2, $t0, $s2 sub $t3, $t0, $s3 srl $t4, $t0, 2 Start numbering the cycles with 1 when the add instruction enters the IF stage. i) For this part, assume that the datapath is broken and there is no forwarding / stalling. What are the values of $t0 to $t4 at the end of cycle 7? Pipelining and Hazards (2/5) Consider the 5-stage single-issue pipelined MIPS datapath consisting of Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Mem, and Write-Back (WB). You are given: # $s0 to $s3 = 56, 30, 30, 7 # $t0 to $t4 = 7, 7, 7, 7, 7 add $t0, $s0, $0 and $t1, $t0, $s1 or $t2, $t0, $s2 sub $t3, $t0, $s3 srl $t4, $t0, 2 Start numbering the cycles with 1 when the add instruction enters the IF stage. ii) For this part, assume that the datapath is broken and there is no forwarding / stalling. What are the values of $t0 to $t4 at the end of cycle 8? Pipelining and Hazards (3/5) Consider the 5-stage single-issue pipelined MIPS datapath consisting of Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Mem, and Write-Back (WB). You are given: # $s0 to $s3 = 56, 30, 30, 7 # $t0 to $t4 = 7, 7, 7, 7...
View Full Document

This note was uploaded on 09/20/2013 for the course CS 61A taught by Professor Harvey during the Fall '08 term at University of California, Berkeley.

Ask a homework question - tutors are online