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Unformatted text preview: de with the same output as
the initial serial code. For convenience: ogtn is the same as omp_get_thread num and
ognt is the same as omp_get_num_threads
Note: parallel/critical block around “...” => #pragma omp parallel/critical { … }
ii) Serial: for(int i = 0; i < m; i += 1) {
total += i;
res[i] = total;
}
Parallel: 0 #pragma omp parallel
1{
2 for(int i = ogtn(); i < m; i += ognt())
3{
4
total += i;
5
res[i] = total;
6}
7}
a) Add a critical block around lines 26
b) Add a critical block around lines 45
c) Add a critical block around line 4
d) The parallel code returns the correct result the fastest without adding anything
e) None of the above cause the code to return the correct result. FSMs, Boolean Logic, Timing (1/6)
You are an intern at a massive hardware firm. Your first
task is to design an “odd counter” circuit that receives a
single bit input every cycle and outputs a single bit every
cycle. It outputs a 1 if and only if it has seen an odd
number of ones AND an odd number of zeros. It starts in
a state where it has seen an even number of ones and
an even number of zeros (remember, zero is an even
number). As an example,
the input:
I: 1 1 0 1 1 1 0 0 0 1 0 1 1 0 0
will produce the output:
O: 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 FSMs, Boolean Logic, Timing (2/6)
The FSM outputs a 1 if and only if it has seen an odd
number of ones AND an odd number of zeroes. a) Complete the FSM diagram: S00 S10 S01 S11 FSMs, Boolean Logic, Timing (3/6)
The FSM outputs a 1 if and only if it has seen an odd
number of ones AND an odd number of zeroes. b) Complete the truth table: FSMs, Boolean Logic, Timing (4/6)
c) Rebuild this circuit with the fewest gates,
using ONLY AND, OR and NOT gates. FSMs, Boolean Logic, Timing (5/6)
d) Your boss wants you to choose an XOR gate for the
circuit below: The clock speed is 2GHz, the setup, hold,
and clocktoq times of the register are 40, 70, and 60
picoseconds (1012s) respectively.
What range of XOR gate delays is acceptable?
E.g., “at least W ps”, “at most X ps”, or “Y to Z ps”. FSMs, Boolean Logic, Timing (6/6)
e) You’re asked to create all the unique 3to2
circuits (i.e., 3 inputs: I2,I1,I0 and 2 outputs),
with one minor catch. Your circuit must ignore
the value of I1 if the value of I2 is 1. How many
different circuits will you have to make? Use
IEC terminology, like 128 mebicircuits, 512
tebicircuits, etc. Datapath and Control (1/5)
On the right is the
singlecycle MIPS
datapath (no
pipelining). Modify
the diagram using
adders, shifters,
mux chips, wires,
and new control
signals to implement
addpr. If necessary
you may replace original labels.
addpr  almost identical to addi, but: stores into the rt
register, the sum of the immediate and the value of the register
specified by the lowest 5 bits in memory at the address
specified by the pointer stored in the rt register. Datapath and Control (2/5)
On the right is the
singlecycle MIPS
datapath (no
pipelining). Modify
the diagram using
adders, shift...
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 Fall '08
 Harvey

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