Assumeournewspecialregistershavebeentypedefedsothatyou

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Unformatted text preview: ers are read during ID and written during WB. a) As a reminder, Tc stands for “time between completions of instructions.” Given the following _____________ datapath stage times, what is the ratio Tc,single‐cycle/Tc,pipelined? IF 200 ps ID 100 ps EX 400 ps MEM 200 ps WB 100 ps b) Count the number of the different types of potential hazards found in the code above: Structural: _____________ Data: _____________ Control: _____________ 1 0 Login: cs61c‐____ For the following questions, examine a SINGLE ITERATION of the loop (do not consider the jr). c) With no optimizations, how many clock cycles does our 5‐stage pipelined datapath take in one loop iteration (end your count exactly on completion of j)? _____________ d) How many clock cycles LESS would be taken if we had FORWARDING? _____________ e) Assuming that we introduce both FORWARDING and DELAY SLOTS, describe independent changes to integrate that will reduce the total clock cycles taken. Changes include replacing or moving instructions. You may not need all spaces given. Instr ______ ________________________________________________________________________ ______ ________________________________________________________________________ ______ ________________________________________________________________________ ______ ________________________________________________________________________ ______ Change ________________________________________________________________________ 11 12 Login: cs61c‐____ Question 7: Conditional Wiring (10 points, 20 minutes) Assume our MIPS machine is implemented as a single‐cycle datapath. Your job is to provide new datapath and control elements that can implement store‐conditional instruction (the implementation of load‐link is provided for you). In particular, the load‐link and store‐conditional should be implemented as: LL: R[rt] <- M[sign(imm) + R[rs]] LLbit <- 1 SC: if LLbit: M[sign(imm) + R[rs]] <- R[rt]; Reset other processor’s LLbit R[rt] <- {31 zeros, LLbit} Modify the picture on the opposite page and list the changes you made here (you may not need all the given lines). You cannot modify the pre‐existing datapath components besides the wires: 1. ________________________________________________________________________ 2. ________________________________________________________________________ 3. ________________________________________________________________________ 4. ________________________________________________________________________ 5. ________________________________________________________________________ 6. ________________________________________________________________________ 7. ________________________________________________________________________ 8. ________________________________________________________________________ Now state what values of these control signals should be {0,1, X for “don’t care,” or any other intuitive names}, plus for any new signals you may have created. RegDst RegWr nPC_sel E...
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