ia-32_instruction-set-ref_a-m

263 source operand 263 otherwise set to 0 undefined

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Unformatted text preview: of the FPU register stack are stored in the 80 bytes immediately following the operating environment image. The FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE instruction. If one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be generated. To avoid raising exceptions when loading a new operating environment, clear all the exception flags in the FPU status word that is being loaded. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation FPUControlWord SRC[FPUControlWord]; FPUStatusWord SRC[FPUStatusWord]; FPUTagWord SRC[FPUTagWord]; FPUDataPointer SRC[FPUDataPointer]; FPUInstructionPointer SRC[FPUInstructionPointer]; FPULastInstructionOpcode SRC[FPULastInstructionOpcode]; ST(0) SRC[ST(0)]; ST(1) SRC[ST(1)]; ST(2) SRC[ST(2)]; ST(3) SRC[ST(3)]; ST(4) SRC[ST(4)]; ST(5) SRC[ST(5)]; 3-368 Vol. 2 INSTRUCTION SET REFERENCE, A-M ST(6) SRC[ST(6)]; ST(7) SRC[ST(7)]; FPU Flags Affected The C0, C1, C2, C3 flags are loaded. Floating-Point Exceptions None; however, this operation might unmask an existing exception that has been detected but not generated, because it was masked. Here, the exception is generated at the completion of the instruction. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Vol. 2 3-369 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-370 Vol. 2 INSTRUCTION SET REFERENCE, A-M FSAVE/FNSAVE--Store x87 FPU State Opcode 9B DD /6 Instruction FSAVE m94/108byte 64-...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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