ia-32_instruction-set-ref_a-m

4 152 psllw pslld and psllq instruction operation

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Unformatted text preview: ing 64-bit Operand . . . . . . . 4-171 PSRAW and PSRAD Instruction Operation Using a 64-bit Operand . . . . . . . . . . . . 4-176 PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand . . . . . . 4-183 PUNPCKHBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . 4-202 PUNPCKLBW Instruction Operation Using 64-bit Operands. . . . . . . . . . . . . . . . . . . 4-207 SHUFPD Shuffle Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-304 SHUFPS Shuffle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307 UNPCKHPD Instruction High Unpack and Interleave Operation . . . . . . . . . . . . . . . 4-382 UNPCKHPS Instruction High Unpack and Interleave Operation . . . . . . . . . . . . . . . 4-385 UNPCKLPD Instruction Low Unpack and Interleave Operation . . . . . . . . . . . . . . . . 4-388 UNPCKLPS Instruction Low Unpack and Interleave Operation . . . . . . . . . . . . . . . . 4-391 ModR/M Byte nnn Field (Bits 5, 4, and 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-19 General Machine Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 TABLES Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. 16-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 32-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 32-Bit Addressing Forms with the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 REX Prefix Fields [BITS: 0100WRXB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 Special Cases of REX Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13 Direct Memory Offset Form of MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14 RIP-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15 Vol. 2A xv CONTENTS PAGE Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 3-19. Table 3-20. Table 3-21. Table 3-22. Table 3-23. Table 3-24. Table 3-25. Table 3-26. Table 3-27. Table 3-28. Table 3-29. Table 3-30. Table 3-31. Table 3-32. Table 3-33. Table 3-34. Table 3-35. Table 3-36. Table 3-37. Table 3-38. Table 3-39. Table 3-40. Table 3-41. Table 3-42. Table 3-43. Table 3-44. Table 3-45. Register Codes Associated With +rb, +rw, +rd, +ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Range of Bit Positions Specified by Bit Offset Operands . . . . . . . . . . . . . . . . . . . . . . 3-11 Intel 64 and IA...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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