ia-32_instruction-set-ref_a-m

xmm2m128630 xmm2m12812764 intel cc compiler

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Unformatted text preview: INSTRUCTION SET REFERENCE, A-M In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation xmm1[31:0] = xmm1[31:0] + xmm1[63:32]; xmm1[63:32] = xmm1[95:64] + xmm1[127:96]; xmm1[95:64] = xmm2/m128[31:0] + xmm2/m128[63:32]; xmm1[127:96] = xmm2/m128[95:64] + xmm2/m128[127:96]; Intel C/C++ Compiler Intrinsic Equivalent HADDPS __m128 _mm_hadd_ps(__m128 a, __m128 b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. Numeric Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM #XM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. 3-436 Vol. 2 INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #XM #UD If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #XM #UD If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM For a page fault. If CR0.TS[bit 3] = 1. Vol. 2 3-437 INSTRUCTION SET REFERENCE, A-M #XM #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID feature flag SSE3 is 0. 3-438 Vol. 2 INSTRU...
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