ia-32_instruction-set-ref_a-m

0 to ffffh nm ud if cr0tsbit 3 1 if cr0embit 2

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Unformatted text preview: rce operand is written to the low doubleword of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits. In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. 3-606 Vol. 2 INSTRUCTION SET REFERENCE, A-M Operation MOVD instruction when destination operand is MMX technology register: DEST[31:0] SRC; DEST[63:32] 00000000H; MOVD instruction when destination operand is XMM register: DEST[31:0] SRC; DEST[127:32] 000000000000000000000000H; MOVD instruction when source operand is MMX technology or XMM register: DEST SRC[31:0]; MOVQ instruction when destination operand is XMM register: DEST[63:0] SRC[63:0]; DEST[127:64] 0000000000000000H; MOVQ instruction when destination operand is r/m64: DEST[63:0] SRC[63:0]; MOVQ instruction when source operand is XMM register or r/m64: DEST SRC[63:0]; Intel C/C++ Compiler Intrinsic Equivalent MOVD MOVD MOVD MOVD __m64 _mm_cvtsi32_si64 (int i ) int _mm_cvtsi64_si32 ( __m64m ) __m128i _mm_cvtsi32_si128 (int a) int _mm_cvtsi128_si32 ( __m128i a) Flags Affected None. SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) If the destination operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. Vol. 2 3-607 INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM #MF #PF(fault-code) #AC(0) If CR0.TS[bit 3] = 1. (MMX register operations only) If there is a pending FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #UD If any part of the operand lies outside of the effective address space from 0 to FFFFH. If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM #MF If CR0.TS[bit 3] = 1. (MMX register operations only) If there is a pending FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Pro...
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