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Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
Same exceptions as in Protected Mode. Vol. 2 3-287 INSTRUCTION SET REFERENCE, A-M FADD/FADDP/FIADD--Add
Opcode D8 /0 DC /0 D8 C0+i DC C0+i DE C0+i DE C1 DA /0 DE /0 Instruction FADD m32fp FADD m64fp FADD ST(0), ST(i) FADD ST(i), ST(0) FADDP ST(i), ST(0) FADDP FIADD m32int FIADD m16int 64-Bit Mode Valid Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Valid Description Add m32fp to ST(0) and store result in ST(0). Add m64fp to ST(0) and store result in ST(0). Add ST(0) to ST(i) and store result in ST(0). Add ST(i) to ST(0) and store result in ST(i). Add ST(0) to ST(i), store result in ST(i), and pop the register stack. Add ST(0) to ST(1), store result in ST(1), and pop the register stack. Add m32int to ST(0) and store result in ST(0). Add m16int to ST(0) and store result in ST(0). Description
Adds the destination and source operands and stores the sum in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format. The no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The one-operand version adds the contents of a memory location (either a floating-point or an integer value) to the contents of the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i) register or vice versa. The value in ST(0) can be doubled by coding: FADD ST(0), ST(0); The FADDP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. (The nooperand version of the floating-point add instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.) The FIADD instructions convert an integer source operand to double extended-precision floating-point format before performing the addition. The table on the following page shows the results obtained when adding various classes of numbers, assuming that neither overflow nor underflow occurs. 3-288 Vol. 2 INSTRUCTION SET REFERENCE, A-M When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward - mode, in which case the result is -0. When the source operand is an integer 0, it is treated as a +0. When both operand are infinities of the same sign, the result is of the expected sign. If both operands are infinities of opposite signs, an invalid-operation exception is generated. See Table 3-23. Table 3-23. FADD/FADDP/FIADD Results
DEST - - -F or -I SRC -0 +0 +F or +I + NaN - - - - - * NaN -F - -F DEST DEST F or 0 + NaN -0 - SRC -0 0 SRC + NaN +...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11