ia-32_instruction-set-ref_a-m

Ia-32_instruction-set-ref_a-m

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Unformatted text preview: n to MMX technology and does not take x87 FPU exceptions. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]); DEST[127:64] Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]); Intel C/C++ Compiler Intrinsic Equivalent CVTPI2PD __m128d _mm_cvtpi32_pd(__m64 a) SIMD Floating-Point Exceptions None. Vol. 2 3-203 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #MF #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #MF #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 3-204 Vol. 2 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #MF #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-205 INSTRUCTION SET REFERENCE, A-M CVTPI2PS--Convert Packed Doubleword Integers to Packed SinglePrecision Floating-Point Values Opcode 0F 2A /r Instruction CVTPI2PS xmm, mm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two signed doubleword integers from mm/m64 to two single-precision floating-point values in xmm. Description Converts two packed signed doubleword integers in the source operand (second operand) to two packed single-precision floating-point values in the destination operand (first operand). The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an XMM register. The results are stored in the low quadword of the destination operand, and the high quadword remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. This instruction causes a transition from x87 FPU to MMX technology operation...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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