ia-32_instruction-set-ref_a-m

25 0 virtual 8086 mode exceptions same exceptions as

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Unformatted text preview: , FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) #SS(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. 3-682 Vol. 2 INSTRUCTION SET REFERENCE, A-M #PF(fault-code) #AC(0) If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-683 INSTRUCTION SET REFERENCE, A-M MULPD--Multiply Packed Double-Precision Floating-Point Values 64Bit Mode Valid Opcode 66 0F 59 /r Instruction MULPD xmm1, xmm2/m128 Compat/ Leg Mode Valid Description Multiply packed double-precision floating-point values in xmm2/m128 by xmm1. Description Performs a SIMD multiply of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the packed double-precision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Figure 11-3 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD double-precision floating-point operation. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] DEST[63:0] SRC[63:0]; DEST[127:64] DEST[127:64] SRC[127:64]; Intel C/C++ Compiler Intrinsic Equivalent MULPD __m128d _mm_mul_pd (m128d a, m128d b) SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. 3-684 Vol. 2 INSTRUCTION SET REFERENCE, A-M #XM #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If...
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