3 1 if an unmasked simd floating point exception and

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Unformatted text preview: Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. 3-586 Vol. 2 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #XM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-587 INSTRUCTION SET REFERENCE, A-M MONITOR--Set Up Monitor Address Opcode OF 01 C8 Instruction MONITOR 64-Bit Mode Valid Compat/ Leg Mode Valid Description Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a write-back memory caching type. The default address is DS:EAX. Description The MONITOR instruction arms address monitoring hardware using an address specified in EAX (the address range that the monitoring hardware checks for store operations can be determined by using CPUID). A store to an address within the specified address range triggers the monitoring hardware. The state of monitor hardware is used by MWAIT. The content of EAX is an effective address. By default, the DS segment is used to create a linear address that is monitored. Segment overrides can be used. ECX and EDX are also used. They communicate other information to MONITOR. ECX specifies optional extensions. EDX specifies optional hints; it does not change the architectural behavior of the instruction. For the Pentium 4 processor (family 15, model 3), no extensions or hints are defined. Undefined hints in EDX are ignored by the processor; undefined extensions in ECX raises a general protection fault. The address range must use memory of the write-back type. Only write-back memory will correctly trigger the monitoring hardware. Additional information on determining what address range to use in order to prevent false wake-ups is described in Chapter 7, "Multiple-Processor Management" of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. The MONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruction can be used at all privilege levels and is subject to the permission checking and faults associated with a byte load. Like a load, MONITOR sets the A-bit but not the D-bit in page tables. The MONITOR CPUID feature flag (ECX bit 3; CPUID executed EAX = 1) indicates the availability of MONITOR and MWAIT in the processor. When set, the unconditional execution of MONITOR is supported at privilege levels 0; conditional execution is...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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