ia-32_instruction-set-ref_a-m

3 14 processor type field type original oem processor

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Unformatted text preview: che line flushed with CLFLUSH instruction in 8-byte increments. This field was introduced in the Pentium 4 processor. 3-170 Vol. 2 INSTRUCTION SET REFERENCE, A-M Local APIC ID (high byte of EBX) -- this number is the 8-bit ID that is assigned to the local APIC on the processor during power up. This field was introduced in the Pentium 4 processor. INPUT EAX = 1: Returns Feature Information in ECX and EDX When CPUID executes with EAX set to 1, feature information is returned in ECX and EDX. Figure 3-6 and Table 3-15 show encodings for ECX. Figure 3-7 and Table 3-16 show encodings for EDX. For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags. NOTE Software must confirm that a processor feature is present using feature flags returned by CPUID prior to using the feature. Software should not depend on future offerings retaining all features. Figure 3-6. Extended Feature Information Returned in the ECX Register Vol. 2 3-171 INSTRUCTION SET REFERENCE, A-M Table 3-15. More on Extended Feature Information Returned in the ECX Register Bit # 0 1-2 3 4 Mnemonic SSE3 Reserved MONITOR DS-CPL Description Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this technology. Reserved MONITOR/MWAIT. A value of 1 indicates the processor supports this feature. CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL. Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology Reserved Enhanced Intel SpeedStep technology. A value of 1 indicates that the processor supports this technology. Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology. A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction extensions are not present in the processor L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of 0 indicates this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details. Reserved CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the "CMPXCHG8B/CMPXCHG16B--Compare and Exchange Bytes" section in this chapter for a description. xTPR Update Control. A value of 1 indicates that the processor supports changing IA32_MISC_ENABLES[bit 23]. Reserved 5 6 7 8 9 VMX Reserved EST TM2 SSSE3 10 CNXT-ID 11-12 13 Reserved CMPXCHG16B 14 31 - 15 xTPR Update Control Reserved 3-172 Vol. 2 INSTRUCTION SET REFERENCE, A-M Figure 3-7. Feature Information Returned in the EDX Register Table 3-16. More on Feature Information Returned in the EDX Register Bit # 0 1 Mnemonic FPU VME Description Floating Point Unit On-Chip. The processor contains an x87 FPU. Virtual 8086 Mode Enhancements. Virtual 808...
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