ia-32_instruction-set-ref_a-m

3 3 516 vol 2 instruction set reference a m lddqu load

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Unformatted text preview: scription of the MXCSR register and its contents. The LDMXCSR instruction is typically used in conjunction with the STMXCSR instruction, which stores the contents of the MXCSR register in memory. The default MXCSR value at reset is 1F80H. If a LDMXCSR instruction clears a SIMD floating-point exception mask bit and sets the corresponding exception flag bit, a SIMD floating-point exception will not be immediately generated. The exception will be generated only upon the execution of the next SSE or SSE2 instruction that causes that particular SIMD floating-point exception to be reported. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation MXCSR m32; C/C++ Compiler Intrinsic Equivalent _mm_setcsr(unsigned int i) Numeric Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments. For an attempt to set reserved bits in MXCSR. #SS(0) #PF(fault-code) #NM For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. 3-520 Vol. 2 INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to FFFFH. For an attempt to set reserved bits in MXCSR. #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For an attempt to set reserved bits in MXCSR. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-521 INSTRUCTION SET REFERENCE, A-M LDS/LES/LFS/LGS/LSS--Load Far Pointer Opcode C5 /r C5 /r 0F B2 /r 0F B2 /r REX + 0F B2 /r C4 /r C4 /r 0F B4 /r 0F B4 /r REX + 0F B4 /r 0F B5 /r 0F B5 /r REX + 0F B5 /r Instruction LDS r16,m16:16 LDS r32,m16:32 LSS r16,m16:16 LSS r32,m16:32 LSS r64,m16:64 LES r16,m16:16 LES r32,m16:32 LFS r16,m16:16 LFS r32,m16:32 LFS r64,m16:64 LGS r16,m16:16 LGS r32,m16:32 LGS r64,m16:64 64-Bit Mode Invalid Invalid Valid Valid Valid Invalid Invalid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid N.E. Valid Valid Valid Valid N.E. Valid Valid N.E. Description Load DS:r16 with far pointer from memory. Load DS:r32 with far po...
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