ia-32_instruction-set-ref_a-m

32 kbyte 4 way set associative 64 byte line size

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Unformatted text preview: and TLBs when the CPUID executes with an input value of 2: EAX EBX ECX EDX 66 5B 50 01H 0H 0H 00 7A 70 00H Which means: The least-significant byte (byte 0) of register EAX is set to 01H. This indicates that CPUID needs to be executed once with an input value of 2 to retrieve complete information about caches and TLBs. The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register contains valid 1-byte descriptors. Bytes 1, 2, and 3 of register EAX indicate that the processor has: -- 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4MByte pages. -- 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages. -- 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size. The descriptors in registers EBX and ECX are valid, but contain NULL descriptors. Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has: -- 00H - NULL descriptor. -- 70H - Trace cache: 12 K-op, 8-way set associative. -- 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size. -- 00H - NULL descriptor. Vol. 2 3-179 INSTRUCTION SET REFERENCE, A-M INPUT EAX = 4: Returns Deterministic Cache Parameters for Each Level When CPUID executes with EAX set to 4 and ECX contains an index value, the processor returns encoded data that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid index values start from 0. Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally defined fields reported by deterministic cache parameters are documented in Table 3-12. The CPUID leaf 4 also reports information about maximum number of cores in a physical package. This information is constant for all valid index values. Software can query maximum number of cores per physical package by executing CPUID with EAX=4 and ECX=0. INPUT EAX = 5: Returns MONITOR and MWAIT Features When CPUID executes with EAX set to 5, the processor returns information about features available to MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power management. See Table 3-12. INPUT EAX = 6: Returns Thermal and Power Management Features When CPUID executes with EAX set to 6, the processor returns information about thermal and power management features. See Table 3-12. INPUT EAX = 10: Returns Architectural Performance Monitoring Features When CPUID executes with EAX set to 10, the processor returns information about support for architectural performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see Table 3-12) is greater than Pn 0. See Table...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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