ia-32_instruction-set-ref_a-m

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Unformatted text preview: ort addresses 0 to 255 to be accessed. When accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port, the operand-size attribute determines the port size. At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0. This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 13, "Input/Output," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more information on accessing I/O ports in the I/O address space. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation IF ((PE = 1) and ((CPL > IOPL) or (VM = 1))) THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *) IF (Any I/O Permission Bit for I/O port being accessed = 1) THEN (* I/O operation is not allowed *) #GP(0); ELSE ( * I/O operation is allowed *) DEST SRC; (* Read from selected I/O port *) Vol. 2 3-457 INSTRUCTION SET REFERENCE, A-M FI; ELSE (Real Mode or Protected Mode with CPL IOPL *) DEST SRC; (* Read from selected I/O port *) FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the corresponding I/O permission bits in TSS for the I/O port being accessed is 1. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions #GP(0) #PF(fault-code) If any of the I/O permission bits in the TSS for the I/O port being accessed is 1. If a page fault occurs. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the corresponding I/O permission bits in TSS for the I/O port being accessed is 1. 3-458 Vol. 2 INSTRUCTION SET REFERENCE, A-M INC--Increment by 1 Opcode FE /0 REX + FE /0 FF /0 FF /0 REX.W + FF /0 40+ rw** 40+ rd Instruction INC r/m8 INC r/m8* INC r/m16 INC r/m32 INC r/m64 INC r16 INC r32 64-Bit Mode Valid Valid Valid Valid Valid N.E. N.E. Compat/ Leg Mode Valid N.E. Valid Valid N.E. Valid Valid Description Increment r/m byte by 1. Increment r/m byte by 1. Increment r/m word by 1. Increment r/m doubleword by 1. Increment r/m quadword by 1. Increment word register by 1. Increment doubleword register by 1. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. ** 40H through 47H are REX prefixes in 64-bit mode. Description Adds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the CF flag.) This instruction can be used with a LOCK prefix to allow the instr...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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