ia-32_instruction-set-ref_a-m

Ac0 if a memory address referencing the ss segment is

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Unformatted text preview: CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) GP(0) #NM #XM #UD If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. Vol. 2 3-685 INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-686 Vol. 2 INSTRUCTION SET REFERENCE, A-M MULPS--Multiply Packed Single-Precision Floating-Point Values 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 0F 59 /r Instruction MULPS xmm1, xmm2/m128 Description Multiply packed single-precision floating-point values in xmm2/mem by xmm1. Description Performs a SIMD multiply of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the packed single-precision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Figure 10-5 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD single-precision floating-point operation. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[31:0] DEST[31:0] SRC[31:0]; DEST[63:32] DEST[63:32] SRC[63:32]; DEST[95:64] DEST[95:64] SRC[95:64]; DEST[127:96] DEST[127:96] SRC[127:96]; Intel C/C++ Compiler Intrinsic Equivalent MULPS __m128 _mm_mul_ps(__m128 a, __m128 b) SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. Vol. 2 3-687 INSTRUCTION SET REFERENCE, A-M #XM #UD If an unmasked SIMD floating-point exception and CR4.OSX...
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