ia-32_instruction-set-ref_a-m

Ax imm16 add eax imm32 add rax imm32 64 bit mode

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Unformatted text preview: 80 /0 ib REX + 80 /0 ib 81 /0 iw 81 /0 id REX.W + 81 /0 id ADD r/m8, imm8 ADD r/m8*, imm8 ADD r/m16, imm16 ADD r/m32, imm32 ADD r/m64, imm32 ADD r/m16, imm8 ADD r/m32, imm8 ADD r/m64, imm8 ADD r/m8, r8 ADD r/m8*, r8* ADD r/m16, r16 ADD r/m32, r32 ADD r/m64, r64 ADD r8, r/m8 ADD r8*, r/m8* ADD r16, r/m16 ADD r32, r/m32 ADD r64, r/m64 Valid Valid Valid Valid Valid Valid N.E. Valid Valid N.E. 83 /0 ib 83 /0 ib REX.W + 83 /0 ib 00 /r REX + 00 /r 01 /r 01 /r REX.W + 01 /r 02 /r REX + 02 /r 03 /r 03 /r REX.W + 03 /r Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid N.E. Valid N.E. Valid Valid N.E. Valid N.E. Valid Valid N.E. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. 3-30 Vol. 2 INSTRUCTION SET REFERENCE, A-M Description Adds the destination operand (first operand) and the source operand (second operand) and then stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is signextended to the length of the destination operand format. The ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer operands and sets the OF and CF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result. This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation DEST DEST + SRC; Flags Affected The OF, SF, ZF, AF, CF, and PF flags are set according to the result. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-31 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the C...
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