ia-32_instruction-set-ref_a-m

Contd initial eax value 04h note 04h output depends

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Unformatted text preview: ts treating interrupts as break-event for MWAIT, even when interrupts disabled Bits 31 - 02: Reserved Bits 03 - 00: Number of C0* sub C-states supported using MWait Bits 07 - 04: Number of C1* sub C-states supported using MWAIT Bits 11 - 08: Number of C2* sub C-states supported using MWAIT Bits 15 - 12: Number of C3* sub C-states supported using MWAIT Bits 19 - 16: Number of C4* sub C-states supported using MWAIT Bits 31 - 20: Reserved = 0 * The definition of C0 through C4 states for MWAIT extension are processor-specific C-states, not ACPI C-states. Thermal and Power Management Leaf 6H EAX EBX ECX Bits 00: Digital temperature sensor is supported if set Bits 31 - 01: Reserved Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor Bits 31 - 04: Reserved Bits 00: ACNT/MCNT. The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of expected processor performance at frequency specified in CPUID Brand String Bits 31 - 01: Reserved = 0 Reserved = 0 EBX ECX EDX EDX Architectural Performance Monitoring Leaf 3-164 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value 0AH EAX Information Provided about the Processor Bits 07 - 00: Version ID of architectural performance monitoring Bits 15- 08: Number of general-purpose performance monitoring counter per logical processor Bits 23 - 16: Bit width of general-purpose, performance monitoring counter Bits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring events Bit 0: Core cycle event not available if 1 Bit 1: Instruction retired event not available if 1 Bit 2: Reference cycles event not available if 1 Bit 3: Last-level cache reference event not available if 1 Bit 4: Last-level cache misses event not available if 1 Bit 5: Branch instruction retired event not available if 1 Bit 6: Branch mispredict retired event not available if 1 Bits 31- 07: Reserved = 0 Reserved = 0 Bits 04 - 00: Number of fixed-function performance counters (if Version ID > 1) Bits 12- 05: Bit width of fixed-function performance counters (if Version ID > 1) Reserved = 0 EBX ECX EDX Extended Function CPUID Information 80000000H EAX EBX ECX EDX Maximum Input Value for Extended Function CPUID Information (see Table 3-13). Reserved Reserved Reserved Vol. 2 3-165 INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value 80000001H EAX EBX ECX EDX Information Provided about the Processor Extended Processor Signature and Extended Feature Bits. Reserved Bit 0: LAHF/SAHF available in 64-bit mode Bits 31-1 Reserved Bits 10-0: Reserved Bit 11: SYSCALL/SYSRET available (when in 64-bit mode) Bits 19-12: Reserved = 0 Bit 20: Execute Disable Bit available Bits 28-21: Reserved = 0 Bit 29: Intel 64 Technology available = 1 Bits 31-30: Reserved = 0 Processor Brand String Processor Brand String Continued Processor Brand Strin...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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