ia-32_instruction-set-ref_a-m

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Unformatted text preview: ot aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Vol. 2 3-193 INSTRUCTION SET REFERENCE, A-M CVTPD2DQ--Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode F2 0F E6 Instruction CVTPD2DQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed doubleprecision floating-point values from xmm2/m128 to two packed signed doubleword integers in xmm1. Description Converts two packed double-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The result is stored in the low quadword of the destination operand and the high quadword is cleared to all 0s. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]); DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64]); DEST[127:64] 0000000000000000H; Intel C/C++ Compiler Intrinsic Equivalent CVTPD2DQ __m128d _mm_cvtpd_epi32(__m128d a) SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. 3-194 Vol. 2 INSTRUCTION SET REFERENCE, A-M #SS(0) #PF(fault-code) #NM #XM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #XM #UD If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0...
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