ia-32_instruction-set-ref_a-m

Dxax edxeax or rdxrax registers dividend by the source

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Unformatted text preview: egister. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #DE #GP If the source operand (divisor) is 0. If the quotient is too large for the designated register. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #DE If the source operand (divisor) is 0. If the quotient is too large for the designated register. 3-264 Vol. 2 INSTRUCTION SET REFERENCE, A-M #GP(0) #SS #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #DE #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If the source operand (divisor) is 0 If the quotient is too large for the designated register. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-265 INSTRUCTION SET REFERENCE, A-M DIVPD--Divide Packed Double-Precision Floating-Point Values Opcode 66 0F 5E /r Instruction DIVPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Divide packed double-precision floatingpoint values in xmm1 by packed doubleprecision floating-point values xmm2/m128. Description Performs a SIMD divide of the two packed double-precision floating-point values in the destination operand (first operand) by the two packed double-precision floatingpoint values in the source operand (second operand), and stores the packed doubleprecision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Chapter 11 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an overview of a SIMD double-precision floating-point operation. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] DEST[63:0] / (SRC[63:0]); DEST[127:64] DEST[127:64] / (SRC[127:64]); Intel C/C++ Compiler Intrinsic Equivalent DIVPD __m128 _mm_div_pd(__m128 a, __m128 b) SIMD Floating-Point Exceptions Overflow, Underflow,...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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