Developers manual volume 2b for information on

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: If the LDT descriptor is not present. If a page fault occurs. Real-Address Mode Exceptions #UD The LLDT instruction is not recognized in real-address mode. Virtual-8086 Mode Exceptions #UD The LLDT instruction is not recognized in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #GP(selector) If a memory address referencing the SS segment is in a noncanonical form. If the current privilege level is not 0. If the memory address is in a non-canonical form. If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT is not a Local Descriptor Table. Segment selector is beyond GDT limit. #NP(selector) #PF(fault-code) If the LDT descriptor is not present. If a page fault occurs. 3-538 Vol. 2 INSTRUCTION SET REFERENCE, A-M LMSW--Load Machine Status Word Opcode 0F 01 /6 Instruction LMSW r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid Description Loads r/m16 in machine status word of CR0. Description Loads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can be a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which contains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are not affected. The operand-size attribute has no effect on this instruction. If the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to switch to protected mode. While in protected mode, the LMSW instruction cannot be used to clear the PE flag and force a switch back to real-address mode. The LMSW instruction is provided for use in operating-system software; it should not be used in application programs. In protected or virtual-8086 mode, it can only be executed at CPL 0. This instruction is provided for compatibility with the Intel 286 processor; programs and procedures intended to run on the Pentium 4, Intel Xeon, P6 family, Pentium, Intel486, and Intel386 processors should use the MOV (control registers) instruction to load the whole CR0 register. The MOV CR0 instruction can be used to set and clear the PE flag in CR0, allowing a procedure or program to switch between protected and real-address modes. This instruction is a serializing instruction. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Note that the operand size is fixed at 16 bits. See "Changes to Instruction Behavior in VMX Non-Root Operation" in Chapter 21 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B, for more information about the behavior of this instruction in VMX non-root operation. Operation CR0[0:3] SRC[0:3]; Flags Affected None. Vol. 2 3-539 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If th...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online