ia-32_instruction-set-ref_a-m

E4 ib e5 ib e5 ib ec ed ed instruction in al imm8 in

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Unformatted text preview: uction to be executed atomically. In 64-bit mode, INC r16 and INC r32 are not encodable (because opcodes 40H through 47H are REX prefixes). Otherwise, the instruction's 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. Operation DEST DEST + 1; AFlags Affected The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result. Vol. 2 3-459 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULLsegment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-460 Vol. 2 INSTRUCTION SET REFERENCE, A-M INS/INSB/INSW/INSD--Input from Port to String Opcode 6C Instruction INS m8, DX 64-Bit Mode Valid Compat/ Leg Mode Valid Description Input byte from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.1 Input word from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.1 Input doubleword from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.1 Input byte from I/O port specified in DX into memory location specified with ES:(E)DI or RDI.1 Input word from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.1 Input doubleword from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.1 6D INS m16, DX Valid Valid 6D INS m32, DX Valid Valid 6C INSB Valid Valid 6D INSW Valid Valid 6D INSD Valid Valid NOTES: 1. n 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported. In non-64-bit mode, only 32-bit (EDI) and 16-bit (DI) address sizes are supported De...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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