ia-32_instruction-set-ref_a-m

Else ud fi else ah eflagssfzf0af0pf1cf fi flags

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Unformatted text preview: ng code segment and (CPL > DPL) or (RPL > DPL) or segment type is not valid for instruction THEN ZF 0 ELSE TEMP Read segment descriptor ; IF OperandSize = 64 THEN DEST (ACCESSRIGHTWORD(TEMP) AND 00000000_00FxFF00H); ELSE (* OperandSize = 32*) DEST (ACCESSRIGHTWORD(TEMP) AND 00FxFF00H); ELSE (* OperandSize = 16 *) DEST (ACCESSRIGHTWORD(TEMP) AND FF00H); FI; FI; FI: Flags Affected The ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is set to 0. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3. Vol. 2 3-515 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #UD The LAR instruction is not recognized in real-address mode. Virtual-8086 Mode Exceptions #UD The LAR instruction cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If the memory operand effective address referencing the SS segment is in a non-canonical form. If the memory operand effective address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3. 3-516 Vol. 2 INSTRUCTION SET REFERENCE, A-M LDDQU--Load Unaligned Integer 128 Bits Opcode F2 0F F0 /r Instruction LDDQU xmm1, mem 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load unaligned data from mem and return double quadword in xmm1. Description The instruction is functionally similar to MOVDQU xmm, m128 for loading from memory. That is: 16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched from memory and placed in a destination register (first operand). The source operand need not be aligned on a 16-byte boundary. Up to 32 bytes may be loaded from memory; this is implementation dependent. This instruction may improve performance relative to MOVDQU if the source operand crosses a cache line boundary. In situations that require the data loaded by LDDQU be modified and stored to the same location, use MOVDQU or MOVDQA instead of LDDQU. To move a double quadword to or from memory locations that are known to be aligned on 16-byte boundaries, use the MOVDQA instruction. Implementation Notes If the source is aligned to a 16-byte boundary, based on the implementation, the 16 bytes may be loaded more than once. For that reason, the usage of LDDQU should be avoided when using uncached or write-combining (WC) memory regions. For uncached or WC memory regions, keep using MOVDQU. This instruc...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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