ia-32_instruction-set-ref_a-m

Exceptions gp0 ss0 nm pffault code ac0 if a memory

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Unformatted text preview: -bit mode. Operation FPUControlWord SRC[FPUControlWord]; FPUStatusWord SRC[FPUStatusWord]; FPUTagWord SRC[FPUTagWord]; FPUDataPointer SRC[FPUDataPointer]; FPUInstructionPointer SRC[FPUInstructionPointer]; FPULastInstructionOpcode SRC[FPULastInstructionOpcode]; 3-346 Vol. 2 INSTRUCTION SET REFERENCE, A-M FPU Flags Affected The C0, C1, C2, C3 flags are loaded. Floating-Point Exceptions None; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next "waiting" floating-point instruction. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-347 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-348 Vol. 2 INSTRUCTION SET REFERENCE, A-M FMUL/FMULP/FIMUL--Multiply Opcode D8 /1 DC /1 D8 C8+i DC C8+i DE C8+i DE C9 DA /1 DE /1 Instruction FMUL m32fp FMUL m64fp FMUL ST(0), ST(i) FMUL ST(i), ST(0) FMULP ST(i), ST(0) FMULP FIMUL m32int FIMUL m16int 64-Bit Mode Valid Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Valid Description Multiply ST(0) by m32fp and store result in ST(0). Multiply ST(0) by m64fp and store result in ST(0). Multiply ST(0) by ST(i) and store result in ST(0). Multiply ST(i) by ST(0) and store result in ST(i). Multiply ST(i) by ST(0), store result in ST(i), and pop the register stack. Multiply ST(1) by ST(0), store result in ST(1), and pop the register stack. Multiply ST(0) by m32int and store result in ST(0). Multiply ST(0) by m16int and store...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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