ia-32_instruction-set-ref_a-m

Fi fpu flags affected c1 c0 c2 c3 set to 0 if stack

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Unformatted text preview: int Exceptions #IS Stack overflow occurred. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-326 Vol. 2 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-327 INSTRUCTION SET REFERENCE, A-M FINCSTP--Increment Stack-Top Pointer Opcode D9 F7 Instructio n FINCSTP 64-Bit Mode Valid Compat/ Leg Mode Valid Description Increment the TOP field in the FPU status register. Description Adds one to the TOP field of the FPU status word (increments the top-of-stack pointer). If the TOP field contains a 7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected. This operation is not equivalent to popping the stack, because the tag for the previous top-of-stack register is not marked empty. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation IF TOP = 7 THEN TOP 0; ELSE TOP TOP + 1; FI; FPU Flags Affected The C1 flag is set to 0. The C0, C2, and C3 flags are undefined. Floating-Point Exceptions None. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. 3-328 Vol. 2 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-329 INSTRUCTION SET REFERENCE, A-M FINIT/FN...
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