ia-32_instruction-set-ref_a-m

Fi vol 2 3 251 instruction set reference a m intel cc

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Unformatted text preview: alid Valid N.E. Description DX:AX sign-extend of AX. EDX:EAX sign-extend of EAX. RDX:RAX sign-extend of RAX. Description Doubles the size of the operand in register AX, EAX, or RAX (depending on the operand size) by means of sign extension and stores the result in registers DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction copies the sign (bit 15) of the value in the AX register into every bit position in the DX register. The CDQ instruction copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruction (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position in the RDX register. The CWD instruction can be used to produce a doubleword dividend from a word before word division. The CDQ instruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO instruction can be used to produce a double quadword dividend from a quadword before a quadword division. The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these mnemonics as synonyms (CWD/CDQ) and use the current setting of the operandsize attribute to determine the size of values to be converted, regardless of the mnemonic used. In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO mnemonics reference the same opcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits. 3-254 Vol. 2 INSTRUCTION SET REFERENCE, A-M Operation IF OperandSize = 16 (* CWD instruction *) THEN DX SignExtend(AX); ELSE IF OperandSize = 32 (* CDQ instruction *) EDX SignExtend(EAX); FI; ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*) RDX SignExtend(RAX); FI; FI; Flags Affected None. Exceptions (All Operating Modes) None. Vol. 2 3-255 INSTRUCTION SET REFERENCE, A-M DAA--Decimal Adjust AL after Addition Opcode 27 Instruction DAA 64-Bit Mode Invalid Compat/ Leg Mode Valid Description Decimal adjust AL after addition. Description Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the CF and AF flags are set accordingly. This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode. Operation IF 64-Bit Mode THEN #UD; ELSE old_AL AL; old_CF CF; CF 0; IF (((AL AND 0FH) > 9) or AF = 1)...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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