ia-32_instruction-set-ref_a-m

# Fnsave instruction to be interrupted prior to being

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Unformatted text preview: on and source operands are floating-point values located in registers ST(0) and ST(1), respectively. This instruction provides rapid multiplication or division by integral powers of 2. The following table shows the results obtained when scaling various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-39. FSCALE Results ST(1) - - NaN -F - -0 - +0 - +F - + - NaN NaN NaN NaN NaN NaN NaN NaN ST(0) -F -0 +0 -0 -0 +0 -F -0 +0 -F -0 -F -0 -F -0 - NaN NaN +0 +F + NaN +0 +F + NaN +0 +F + NaN +F + NaN +0 NaN NaN +F + NaN + + NaN NOTES: F Means finite floating-point value. In most cases, only the exponent is changed and the mantissa (significand) remains unchanged. However, when the value being scaled in ST(0) is a denormal value, the mantissa is also changed and the result may turn out to be a normalized number. Similarly, if overflow or underflow results from a scale operation, the resulting mantissa will differ from the source's mantissa. The FSCALE instruction can also be used to reverse the action of the FXTRACT instruction, as shown in the following example: FXTRACT; FSCALE; FSTP ST(1); Vol. 2 3-375 INSTRUCTION SET REFERENCE, A-M In this example, the FXTRACT instruction extracts the significand and exponent from the value in ST(0) and stores them in ST(0) and ST(1) respectively. The FSCALE then scales the significand in ST(0) by the exponent in ST(1), recreating the original value before the FXTRACT operation was performed. The FSTP ST(1) instruction overwrites the exponent (extracted by the FXTRACT instruction) with the recreated value, which returns the stack to its original state with only one register [ST(0)] occupied. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation ST(0) ST(0) 2RoundTowardZero(ST(1)); FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined. Floating-Point Exceptions #IS #IA #D #U #O #P Stack underflow occurred. Source operand is an SNaN value or unsupported format. Source operand is a denormal value. Result is too small for destination format. Result is too large for destination format. Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-376 Vol. 2 INSTRUCTION SET REFERENCE, A-M FSIN--Sine Opcode D9 FE Instruction FSIN 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with its sine. Description Computes the sine of the source operand in register ST(0) and stores the result in ST(0). The source operand must be given in radians and must be within the range - 263 to +263. The following table shows...
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• Winter '11
• Watlins
• X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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