ia-32_instruction-set-ref_a-m

Fpustatusword srcfpustatusword fputagword

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Unformatted text preview: result in ST(0). Description Multiplies the destination and source operands and stores the product in the destination location. The destination operand is always an FPU data register; the source operand can be an FPU data register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format. The no-operand version of the instruction multiplies the contents of the ST(1) register by the contents of the ST(0) register and stores the product in the ST(1) register. The one-operand version multiplies the contents of the ST(0) register by the contents of a memory location (either a floating point or an integer value) and stores the product in the ST(0) register. The two-operand version, multiplies the contents of the ST(0) register by the contents of the ST(i) register, or vice versa, with the result being stored in the register specified with the first operand (the destination operand). The FMULP instructions perform the additional operation of popping the FPU register stack after storing the product. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point multiply instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FMUL rather than FMULP. The FIMUL instructions convert an integer source operand to double extendedprecision floating-point format before performing the multiplication. Vol. 2 3-349 INSTRUCTION SET REFERENCE, A-M The sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multiplied is 0 or . When the source operand is an integer 0, it is treated as a +0. The following table shows the results obtained when multiplying various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-34. FMUL/FMULP/FIMUL Results DEST - - -F + +F +F +0 -0 -F -F - -0 * +0 +0 +0 -0 -0 -0 * NaN +0 * -0 -0 -0 +0 +0 +0 * NaN +F - + - - - NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN + + + * * - - - -F -I SRC -0 +0 +I +F + NaN -F -F -0 +0 +F +F + NaN * * + + + NaN NaN NaN NOTES: F Means finite floating-point value. I Means Integer. * Indicates invalid-arithmetic-operand (#IA) exception. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation IF Instruction = FIMUL THEN DEST DEST ConvertToDoubleExtendedPrecisionFP(SRC); ELSE (* Source operand is floating-point value *) DEST DEST SRC; FI; IF Instruction = FMULP THEN PopRegisterStack; FI; 3-350 Vol. 2 INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined. Floating-Point Exceptions #IS #IA #D #U #O #P Stack underflow occurred. Operand is an SNaN value or unsupported format. One operand is 0 and the other is . Source operand is a denormal value. Result...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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