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Unformatted text preview: Leg Mode Valid Description Return the minimum scalar singleprecision floating-point value between xmm2/mem32 and xmm1. Description
Compares the low single-precision floating-point values in the destination operand (first operand) and the source operand (second operand), and returns the minimum value to the low doubleword of the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. When the source operand is a memory operand, only 32 bits are accessed. The three high-order doublewords of the destination operand remain unchanged. If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is returned. If a value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN version of the SNaN is not returned). If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second operand) be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN and OR. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation
DEST[63:0] IF ((DEST[31:0] = 0.0) AND (SRC[31:0] = 0.0)) THEN SRC[31:0]; ELSE IF (DEST[31:0] = SNaN) THEN SRC[31:0]; FI; ELSE IF SRC[31:0] = SNaN) THEN SRC[31:0]; FI; ELSE IF (DEST[31:0] < SRC[31:0]) THEN DEST[31:0] ELSE SRC[31:0]; FI; FI; (* DEST[127:32] is unchanged *); Intel C/C++ Compiler Intrinsic Equivalent
MINSS __m128d _mm_min_ss(__m128d a, __m128d b) Vol. 2 3-585 INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions
Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions
#GP(0) #SS(0) #PF(fault-code) #NM #XM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand effective address is outside the SS segment limit. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions
GP(0) #NM #XM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions
Same exceptions as in Real Address...
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- Winter '11