ia-32_instruction-set-ref_a-m

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Unformatted text preview: If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-159 INSTRUCTION SET REFERENCE, A-M CPUID--CPU Identification Opcode 0F A2 Instruction CPUID 64-Bit Mode Valid Compat/ Leg Mode Valid Description Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, as determined by input entered in EAX (and, in some cases, ECX). Description The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction operates the same in non64-bit modes and 64-bit mode. CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers. The instruction's output is dependent on the contents of the EAX register upon execution. For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value and the Vendor Identification String in the appropriate registers: MOV EAX, 00H CPUID Table 3-12 shows information returned, depending on the initial value loaded into the EAX register. Table 3-13 shows the maximum CPUID input value recognized for each family of IA-32 processors on which CPUID is implemented. Two types of information are returned: basic and extended function information. If a value is entered for CPUID.EAX is invalid for a particular processor, the data for the highest basic information leaf is returned. For example, using the Intel CoreTM2 Duo processor, the following is true: CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *) CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *) CPUID.EAX = 0BH (* INVALID: Returns the same information as CPUID.EAX = 0AH. *) CPUID.EAX = 80000008H (* Returns virtual/physical address size data. *) CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0AH. *) CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed. 3-160 Vol. 2 INSTRUCTION SET REFERENCE, A-M See also: "Serializing Instructions" in Chapter 7, "Multiple-Processor Management," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) Table 3-12. Information Returned by CPUID Instruction Initial EAX Value 0H EAX EBX ECX EDX EAX EBX Information Provided about the Processor Basic CPUID Information Maximum Input Value for Basic CPUID Information (see Table 3-13) "Genu" "ntel" "ineI" Version Information: Type, Family, Model, and Stepping ID (see Figure 3-5) Bits 7-0: Brand Index Bits 15-8: CLFLUSH line size (Value 8 = cache line...
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