ia-32_instruction-set-ref_a-m

For an illegal memory operand effective address in

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Unformatted text preview: ster operations only) If there is a pending FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-651 INSTRUCTION SET REFERENCE, A-M MOVQ2DQ--Move Quadword from MMX Technology to XMM Register 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode F3 0F D6 Instruction MOVQ2DQ xmm, mm Description Move quadword from mmx to low quadword of xmm. Description Moves the quadword from the source operand (second operand) to the low quadword of the destination operand (first operand). The source operand is an MMX technology register and the destination operand is an XMM register. This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the MOVQ2DQ instruction is executed. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] SRC[63:0]; DEST[127:64] 00000000000000000H; Intel C/C++ Compiler Intrinsic Equivalent MOVQ2DQ __128i _mm_movpi64_pi64 ( __m64 a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. 3-652 Vol. 2 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-653 INSTRUCTION SET REFERENCE, A-M MOVS/MOVSB/MOVSW/MOVSD/MOVSQ--Move Data from String to String \ Opcode A4 Instruction MOVS m8, m8 64-Bit Mode Valid Compat/ Leg Mode Valid A5 MOVS m16, m16 Valid Valid A5 MOVS m32, m32 Valid Valid REX.W + A5 A4 MOVS m64, m64 MOVSB Valid Valid N.E. Valid A5 MOVSW Valid Valid A5 MOVSD Valid Valid REX.W + A5 MOVSQ Valid N.E. Description For legacy mode, Move byte from address DS:(E)SI to ES:(E)DI. For 64-bit mode move byte from address (R|E)SI to (R|E)DI. For legacy mode, move word from address DS:(E)SI to ES:(E)DI. For 64-bit mode move word at address (R|E)SI to (R|E)DI. For legacy mode, move dword from address DS:(E)SI to ES:(E)DI. For 64-bit mode move dword from address (R|E)SI to (R|E)DI. Move qword from address (R|E)SI to (R|E)DI. For legacy mode, Move byte from address DS:(E)SI to ES:(E)DI. For 64-bit mode move byte from address (R|E)SI to (R|E)DI. For legacy mode, move word from address DS:(E)SI to ES:(E)DI. For 64-bit mode move word at address (R|E)SI to (R|E)DI. For legacy mode, move dword from address DS:(E)SI to ES:(E)DI. For 64-bit mode move dword from address (R|E)SI to (R|E)DI. Move qword from address (R|E)SI to (R|E)DI. Descrip...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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