ia-32_instruction-set-ref_a-m

Ia-32_instruction-set-ref_a-m

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Unformatted text preview: ory location specified in the destination operand. The content layout of the 512 byte region depends on whether the processor is operating in non64-bit operating modes or 64-bit sub-mode of IA-32e mode. The operation of FXSAVE in non-64-bit modes are described first. Non-64-Bit Mode Operation Table 3-48 shows the layout of the state information in memory when the processor is operating in legacy modes. Table 3-48. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR Memory Region 15 14 13 CS 12 11 10 9 8 7 FOP Rsrvd 6 5 4 FTW DS ST0/MM0 ST1/MM1 ST2/MM2 ST3/MM3 ST4/MM4 ST5/MM5 ST6/MM6 ST7/MM7 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 3 FSW FPU DP 2 1 FCW 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 Rsrvd FPU IP MXCSR MXCSR_MASK Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3-416 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-48. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR Memory Region (Contd.) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 XMM7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved The destination operand contains the first byte of the memory image, and it must be aligned on a 16-byte boundary. A misaligned destination operand will result in a general-protection (#GP) exception being generated (or in some cases, an alignment check exception [#AC]). The FXSAVE instruction is used when an operating system needs to perform a context switch or when an exception handler needs to save and examine the current state of the x87 FPU, MMX technology, and/or XMM and MXCSR registers. The fields in Table 3-48 are defined in Table 3-49. Table 3-49. Field Definitions Field FCW Definition x87 FPU Control Word (16 bits). See Figure 8-6 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for the layout of the x87 FPU control word. x87 FPU Status Word (16 bits). See Figure 8-4 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for the layout of the x87 FPU status word. FSW Vol. 2 3-417 INSTRUCTION SET REFERENCE, A-M Table 3-49. Field Definitions (Contd.) Field FTW Definition x87 FPU Tag Word (8 bits). The tag information saved here is abridged, as described in the following paragraphs. See Figure 8-7 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for the layout of the x87 FPU tag word. x87 FPU Opcode (16 bits). The lower 11 bits of this field contain the opcode, upper 5 bits are reserved. See Figure 8-8 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for the layout of the x87 FPU opcode field. x87 FPU Instruction Pointer Offset (32 bits). The contents of this field differ depending on the current addressing mode (32-bit or 16-bit) of the processor when the FXSAVE instruction was executed: 32-bit mode -- 32-bit IP offset. 16-bit mode -- low 16 bits are IP offset; high 16 bits are reserve...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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