ia-32_instruction-set-ref_a-m

Gp0 pffault code ud if a memory address referencing

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Unformatted text preview: 1 1 1 IOPL X CPL < CPL < CPL < CPL CPL X X 3 <3 PVI X X 1 X 0 X X X VIP X X X X X X X X VME X X X X X X 1 0 CLI Result IF = 0 IF = 0 VIF = 0 GP Fault GP Fault IF = 0 VIF = 0 GP Fault X X X X 3 <3 <3 NOTES: * X = This setting has no impact. Vol. 2 3-109 INSTRUCTION SET REFERENCE, A-M Operation IF PE = 0 THEN IF 0; (* Reset Interrupt Flag *) ELSE IF VM = 0; THEN IF IOPL CPL THEN IF 0; (* Reset Interrupt Flag *) ELSE IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1)) THEN VIF 0; (* Reset Virtual Interrupt Flag *) ELSE #GP(0); FI; FI; ELSE (* VM = 1 *) IF IOPL = 3 THEN IF 0; (* Reset Interrupt Flag *) ELSE IF (IOPL < 3) AND (VME = 1) THEN VIF 0; (* Reset Virtual Interrupt Flag *) ELSE #GP(0); FI; FI; FI; FI; Flags Affected If protected-mode virtual interrupts are not enabled, IF is set to 0 if the CPL is equal to or less than the IOPL; otherwise, it is not affected. The other flags in the EFLAGS register are unaffected. When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the EFLAGS register, leaving IF unaffected. 3-110 Vol. 2 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. Vol. 2 3-111 INSTRUCTION SET REFERENCE, A-M CLTS--Clear Task-Switched Flag in CR0 Opcode 0F 06 Instruction CLTS 64-Bit Mode Valid Compat/ Leg Mode Valid Description Clears TS flag in CR0. Description Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-address mode to allow initialization for protected mode. The processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU context in multitasking applications. See the description of the TS flag in the section titled "Control Registers" in Chapter 2 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information about this flag. CLTS operation is the same in non-64-bit modes and 64-bit mode. See Chapter 21, "VMX Non-Root Operation," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B, for more information about the behavior of this instruction in VMX non-root operation. Operation CR0.TS[bit 3] 0; Flags Affected The TS flag in CR0 register is cleared. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions #GP...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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