ia-32_instruction-set-ref_a-m

If cpuid feature flag sse3 is 0 vol 2 3 443

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Unformatted text preview: the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Vol. 2 3-447 INSTRUCTION SET REFERENCE, A-M IDIV--Signed Divide Opcode F6 /7 Instruction IDIV r/m8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Signed divide AX by r/m8, with result stored in: AL Quotient, AH Remainder. Signed divide AX by r/m8, with result stored in AL Quotient, AH Remainder. Signed divide DX:AX by r/m16, with result stored in AX Quotient, DX Remainder. Signed divide EDX:EAX by r/m32, with result stored in EAX Quotient, EDX Remainder. Signed divide RDX:RAX by r/m64, with result stored in RAX Quotient, RDX Remainder. REX + F6 /7 IDIV r/m8* Valid N.E. F7 /7 IDIV r/m16 Valid Valid F7 /7 IDIV r/m32 Valid Valid REX.W + F7 /7 IDIV r/m64 Valid N.E. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Description Divides the (signed) value in the AX, DX:AX, or EDX:EAX (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size (dividend/divisor). Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag. In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instruction divides the signed value in RDX:RAX by the source operand. RAX contains a 64-bit quotient; RDX contains a 64-bit remainder. See the summary chart at the beginning of this section for encoding data and limits. See Table 3-55. 3-448 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-55. IDIV Results Operand Size Word/byte Doubleword/word Quadword/doubleword Doublequadword/ quadword Dividend AX DX:AX EDX:EAX RDX:RAX Divisor r/m8 r/m16 r/m32 r/m64 Quotient AL AX EAX RAX Remainder AH DX EDX RDX Quotient Range -128 to +127 -32,768 to +32,767 -231 to 232 - 1 -263 to 264 - 1 Operation IF SRC = 0 THEN #DE; (* Divide error *) FI; IF OperandSize = 8 (* Word/byte operation *) THEN temp AX / SRC; (* Signed division *) IF (temp > 7FH) or (temp < 80H) (* If a positive result is greater than 7FH or a negative result is less than 80H *) THEN #DE; (* Divide error *) ELSE AL temp; AH AX SignedModulus SRC; FI; ELSE IF OperandSize = 16...
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