If a memory operand effective address is outside the

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Unformatted text preview: or in turn contains a pointer to an interrupt or exception handler procedure. In protected mode, the IDT contains an array of 8-byte descriptors, each of which is an interrupt gate, trap gate, or task gate. In real-address mode, the IDT is an array of 4-byte far pointers (2-byte code segment selector and a 2-byte instruction pointer), each of which point directly to a procedure in the selected segment. (Note that in real-address mode, the IDT is called the interrupt vector table, and its pointers are called interrupt vectors.) The following decision table indicates which action in the lower portion of the table is taken given the conditions in the upper portion of the table. Each Y in the lower section of the decision table represents a procedure defined in the "Operation" section for this instruction (except #GP). Table 3-56. Decision Table PE VM IOPL DPL/CPL RELATIONSHIP INTERRUPT TYPE GATE TYPE REAL-ADDRESSMODE PROTECTED-MODE TRAP-ORINTERRUPT-GATE INTER-PRIVILEGELEVEL-INTERRUPT INTRA-PRIVILEGELEVEL-INTERRUPT Y 0 1 DPL< CPL S/W 1 1 DPL> CPL 1 DPL= CPL or C 1 0 1 1 <3 1 1 =3 DPL< CPL & NC Y Task Trap or Interrupt Trap or Trap or Trap or Trap or Interrupt Interrupt Interrupt Interrupt Y Y Y Y Y Y Y Y Y Y Y Y Y 3-466 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-56. Decision Table (Contd.) INTERRUPT-FROMVIRTUAL-8086MODE TASK-GATE #GP NOTES: - Don't Care. Y Yes, action taken. Blank Action not taken. When the processor is executing in virtual-8086 mode, the IOPL determines the action of the INT n instruction. If the IOPL is less than 3, the processor generates a #GP(selector) exception; if the IOPL is 3, the processor executes a protected mode interrupt to privilege level 0. The interrupt gate's DPL must be set to 3 and the target CPL of the interrupt handler procedure must be 0 to execute the protected mode interrupt to privilege level 0. The interrupt descriptor table register (IDTR) specifies the base linear address and limit of the IDT. The initial base address value of the IDTR after the processor is powered up or reset is 0. Y Y Y Y Y Operation The following operational description applies not only to the INT n and INTO instructions, but also to external interrupts and exceptions. IF PE = 0 THEN GOTO REAL-ADDRESS-MODE; ELSE (* PE = 1 *) IF (VM = 1 and IOPL < 3 AND INT n) THEN #GP(0); ELSE (* Protected mode, IA-32e mode, or virtual-8086 mode interrupt *) IF (IA32_EFER.LMA = 0) THEN (* Protected mode, or virtual-8086 mode interrupt *) GOTO PROTECTED-MODE; ELSE (* IA-32e mode interrupt *) GOTO IA-32e-MODE; FI; FI; FI; Vol. 2 3-467 INSTRUCTION SET REFERENCE, A-M REAL-ADDRESS-MODE: IF ((vector_number 4) + 3) is not within IDT limit THEN #GP; FI; IF stack not large enough for a 6-byte return information THEN #SS; FI; Push (EFLAGS[15:0]); IF 0; (* Clear interrupt flag *) TF 0; (* Clear trap flag *) AC 0; (* Clear AC flag *) Push(CS); Push(IP); (* No error codes are pushed *) CS IDT(Descriptor (vector_number 4), selector));...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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