ia-32_instruction-set-ref_a-m

If alignment checking is enabled and an unaligned

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Unformatted text preview: If CR0.TS[bit 3] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0. Real Address Mode Exceptions GP(0) #NM #UD If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If CR0.EM[bit 2] = 1. If CR0.TS[bit 3] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) #NM #UD #PF(fault-code) #AC(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If CR0.EM[bit 2] = 1. If CR0.TS[bit 3] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0. For a page fault. For unaligned memory reference if the current privilege is 3. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Vol. 2 3-337 INSTRUCTION SET REFERENCE, A-M #MF #PF(fault-code) #AC(0) If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-338 Vol. 2 INSTRUCTION SET REFERENCE, A-M FLD--Load Floating Point Value Opcode D9 /0 DD /0 DB /5 D9 C0+i Instructio n FLD m32fp FLD m64fp FLD m80fp FLD ST(i) 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Description Push m32fp onto the FPU register stack. Push m64fp onto the FPU register stack. Push m80fp onto the FPU register stack. Push ST(i) onto the FPU register stack. Description Pushes the source operand onto the FPU register stack. The source operand can be in single-precision, double-precision, or double extended-precision floating-point format. If the source operand is in single-precision or double-precision floating-point format, it is automatically converted to the double extended-precision floating-point format before being pushed on the stack. The FLD instruction can also push the value in a selected FPU register [ST(i)] onto the stack. Here, pushing register ST(0) duplicates the stack top. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation IF SRC is ST(i) THEN temp ST(i); FI; TOP TOP - 1; IF SRC is memory-operand THEN ST(0) ConvertToDoubleExtendedPrecisionFP(SRC); ELSE (* SRC is ST(i) *) ST(0) temp; FI; FPU Flags Affected C1 C0, C2, C3 Set to 1 if stack overflow occurred; otherwise, set to 0. Undefined. Vol. 2 3-339 INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS #IA Stack underflow or overflow occurred. Source operand is an SNaN. Does not occur if the source operand is in double extended-precision floating-point format (FLD m80fp or FLD ST(i)). Source operand is a denormal value. Does not occur if the source operand is in double extended-precision floating-point format. #D Protected Mode Exceptions #GP(0) If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS,...
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