ia-32_instruction-set-ref_a-m

If an unmasked simd floating point exception and

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Unformatted text preview: conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]); (* DEST[127:32] unchanged *) Intel C/C++ Compiler Intrinsic Equivalent CVTSD2SS __m128_mm_cvtsd_ss(__m128d a, __m128d b) SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. Vol. 2 3-221 INSTRUCTION SET REFERENCE, A-M #XM #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #XM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #XM If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. 3-222 Vol. 2 INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-223 INSTRUCTION SET REFERENCE, A-M CVTSI2SD--Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value Opcode F2 0F 2A /r Instruction CVTSI2SD xmm, r/m32 64Bit Mode Valid Compat/ Leg Mode Valid Description Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm. Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm. REX.W + F2 0F 2A /r CVTSI2SD xmm, r/m64 Valid N.E. Description Converts a signed doubleword integer (or signed quadword integer if oper...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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