ia-32_instruction-set-ref_a-m

Ia-32_instruction-set-ref_a-m

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Unformatted text preview: iption Convert four packed singleprecision floating-point values from xmm2/m128 to four packed signed doubleword integers in xmm1. Description Converts four packed single-precision floating-point values in the source operand (second operand) to four packed signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]); DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]); DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64]); DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96]); Intel C/C++ Compiler Intrinsic Equivalent CVTPS2DQ __m128d _mm_cvtps_epi32(__m128d a) SIMD Floating-Point Exceptions Invalid, Precision. Vol. 2 3-209 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM #XM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #XM #UD If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 3-210 Vol. 2 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD fl...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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