ia-32_instruction-set-ref_a-m

If the offset being jumped to is beyond the limits of

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Unformatted text preview: SE IF OperandSize = 64 (* REX.W used *) THEN DEST (* Zero-extended *) temp; FI; ELSE (* OperandSize = 16 *) DEST temp AND FFFFH; FI; FI; Flags Affected The ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is set to 0. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3. Real-Address Mode Exceptions #UD The LAR instruction is not recognized in real-address mode. 3-552 Vol. 2 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #UD The LAR instruction cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If the memory operand effective address referencing the SS segment is in a non-canonical form. If the memory operand effective address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3. Vol. 2 3-553 INSTRUCTION SET REFERENCE, A-M LTR--Load Task Register Opcode 0F 00 /3 Instruction LTR r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load r/m16 into task register. Description Loads the source operand into the segment selector field of the task register. The source operand (a general-purpose register or a memory location) contains a segment selector that points to a task state segment (TSS). After the segment selector is loaded in the task register, the processor uses the segment selector to locate the segment descriptor for the TSS in the global descriptor table (GDT). It then loads the segment limit and base address for the TSS from the segment descriptor into the task register. The task pointed to by the task register is marked busy, but a switch to the task does not occur. The LTR instruction is provided for use in operating-system software; it should not be used in application programs. It can only be executed in protected mode when the CPL is 0. It is commonly used in initialization code to establish the first task to be executed. The operand-size attribute has no effect on this instruction. In 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the 64-bit base. Operation IF SRC is a NULL selector THEN #GP(0); IF SRC(Offset) > descriptor table limit OR IF SRC(type) global THEN #GP(segment selector); FI; Read segment descriptor; IF segment descriptor is not for an available TSS THEN #GP(segment selector); FI; IF segment descriptor is not present THEN #NP(segment selector); FI; TSSsegment...
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