ia-32_instruction-set-ref_a-m

If there is a pending x87 fpu exception if cr0tsbit 3

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Unformatted text preview: address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. 3-200 Vol. 2 INSTRUCTION SET REFERENCE, A-M #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #XM #UD If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-201 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-202 Vol. 2 INSTRUCTION SET REFERENCE, A-M CVTPI2PD--Convert Packed Doubleword Integers to Packed DoublePrecision Floating-Point Values Opcode 66 0F 2A /r Instruction CVTPI2PD xmm, mm/m64* 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed signed doubleword integers from mm/mem64 to two packed doubleprecision floating-point values in xmm. NOTES: * Operation is different for different operand sets; see the Description section. Description Converts two packed signed doubleword integers in the source operand (second operand) to two packed double-precision floating-point values in the destination operand (first operand). The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an XMM register. In addition, depending on the operand configuration: For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPI2PD instruction is executed. For operands xmm, m64: the instruction does not cause a transitio...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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