ia-32_instruction-set-ref_a-m

Languages in chapter 6 of the intel 64 and ia 32

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Unformatted text preview: ns #SS(0) #PF(fault-code) If the memory address is in a non-canonical form. If a page fault occurs or if a write using the final value of the stack pointer (within the current stack segment) would cause a page fault. Vol. 2 3-283 INSTRUCTION SET REFERENCE, A-M F2XM1--Compute 2x1 Opcode D9 F0 Instruction F2XM1 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with (2ST(0) 1). Description Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range 1.0 to +1.0. If the source value is outside this range, the result is undefined. The following table shows the results obtained when computing the exponential value of various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-21. Results Obtained from F2XM1 ST(0) SRC -1.0 to -0 -0 +0 +0 to +1.0 ST(0) DEST -0.5 to -0 -0 +0 +0 to 1.0 Values other than 2 can be exponentiated using the following formula: xy 2(y log2x) This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation ST(0) (2ST(0) - 1); FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined. Floating-Point Exceptions #IS #IA Stack underflow occurred. Source operand is an SNaN value or unsupported format. 3-284 Vol. 2 INSTRUCTION SET REFERENCE, A-M #D #U #P Source is a denormal value. Result is too small for destination format. Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Real-Address Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-285 INSTRUCTION SET REFERENCE, A-M FABS--Absolute Value Opcode D9 E1 Instruction FABS 64Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST with its absolute value. Description Clears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results obtained when creating the absolute value of various classes of numbers. Table 3-22. Results Obtained from FABS ST(0) SRC - -F ST(0) DEST + +F +0 +0 +F + NaN -0 +0 +F + NaN NOTES: F Means finite floating-point value. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation ST(0) |ST(0)|; FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred; otherwise, set to 0. Undefined. Floating-Point Exceptions #IS Stack underflow occurred. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. 3-286 Vol. 2 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Compatibility Mode E...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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