ia-32_instruction-set-ref_a-m

Leaf edx thermal and power management leaf break eax

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: d range for CPUID. *) Vol. 2 3-187 INSTRUCTION SET REFERENCE, A-M EAX Reserved; (* Information returned for highest basic information leaf. *) EBX Reserved; (* Information returned for highest basic information leaf. *) ECX Reserved; (* Information returned for highest basic information leaf. *) EDX Reserved; (* Information returned for highest basic information leaf. *) BREAK; ESAC; Flags Affected None. Exceptions (All Operating Modes) None. NOTE In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated. 3-188 Vol. 2 INSTRUCTION SET REFERENCE, A-M CVTDQ2PD--Convert Packed Doubleword Integers to Packed DoublePrecision Floating-Point Values Opcode F3 0F E6 Instruction CVTDQ2PD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed signed doubleword integers from xmm2/m128 to two packed double-precision floating-point values in xmm1. Description Converts two packed signed doubleword integers in the source operand (second operand) to two packed double-precision floating-point values in the destination operand (first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. When the source operand is an XMM register, the packed integers are located in the low quadword of the register. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]); DEST[127:64] Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]); Intel C/C++ Compiler Intrinsic Equivalent CVTDQ2PD __m128d _mm_cvtepi32_pd(__m128di a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Vol. 2 3-189 INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[b...
View Full Document

Ask a homework question - tutors are online