ia-32_instruction-set-ref_a-m

Leg mode valid description scale st0 by st1

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Unformatted text preview: the results obtained when taking the sine of various classes of numbers, assuming that underflow does not occur. Table 3-40. FSIN Results SRC (ST(0)) - DEST (ST(0)) * -1 to +1 -0 +0 -1 to +1 * NaN -F -0 +0 +F + NaN NOTES: F Means finite floating-point value. * Indicates floating-point invalid-arithmetic-operand (#IA) exception. If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of range. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2 or by using the FPREM instruction with a divisor of 2. See the section titled "Pi" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for in performing such reductions. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Vol. 2 3-377 INSTRUCTION SET REFERENCE, A-M Operation IF ST(0) < 263 THEN C2 0; ST(0) sin(ST(0)); ELSE (* Source operand out of range *) C2 1; FI; FPU Flags Affected C1 C2 C0, C3 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0. Undefined. Floating-Point Exceptions #IS #IA #D #P Stack underflow occurred. Source operand is an SNaN value, , or unsupported format. Source operand is a denormal value. Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-378 Vol. 2 INSTRUCTION SET REFERENCE, A-M FSINCOS--Sine and Cosine Opcode D9 FB Instruction FSINCOS 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compute the sine and cosine of ST(0); replace ST(0) with the sine, and push the cosine onto the register stack. Description Computes both the sine and the cosine of the source operand in register ST(0), stores the sine in ST(0), and pushes the cosine onto the top of the FPU register stack. (This instruction is faster than executing the FSIN and FCOS instructions in succession.) The source operand must be given in radians and must be within the range -263 to +263. The following table shows the results obtained when taking the sine and cosine of various classes of numbers, assuming that underflow does not occur. Table 3-41. FSINCOS Results SRC ST(0) - DEST ST(1) Cosine * -1 to +1 +1 +1 -1 to +1 * NaN ST(0) Sine * -1 to +1 -0 +0 -1 to +1 * NaN -F -0 +0 +F + NaN NOT...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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