ia-32_instruction-set-ref_a-m

Leg mode valid opcode 66 0f 12 r 66 0f 13 r

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Unformatted text preview: l form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-631 INSTRUCTION SET REFERENCE, A-M MOVMSKPD--Extract Packed Double-Precision Floating-Point Sign Mask 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 66 0F 50 /r Instruction MOVMSKPD r32, xmm MOVMSKPD r64, xmm 66 + REX.W 0F 50 /r Valid N.E. Description Extract 2-bit sign mask from xmm and store in r32. Extract 2-bit sign mask from xmm and store in r64. Zero extend 32-bit results to 64-bits. Description Extracts the sign bits from the packed double-precision floating-point values in the source operand (second operand), formats them into a 2-bit mask, and stores the mask in the destination operand (first operand). The source operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored in the 2 low-order bits of the destination operand. In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the instruction to 64-bit operands. See the summary chart at the beginning of this section for encoding data and limits. Operation DEST[0] SRC[63]; DEST[1] SRC[127]; IF DEST = r32 THEN DEST[3:2] ZeroExtend; ELSE DEST[63:2] ZeroExtend; FI; Intel C/C++ Compiler Intrinsic Equivalent MOVMSKPD int _mm_movemask_pd ( __m128 a) SIMD Floating-Point Exceptions None. 3-632 Vol. 2 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-633 INSTRUCTION SET REFERENCE, A-M MOVMSKPS--Extract Packed Single-Precision Floating-Point Sign Mask Compat/ Leg Mode Valid N.E. Opcode 0F 50 /r REX.W + 0F 50 /r Instruction MOVMSKPS r32, xmm MOVMSKPS r64, xmm 64-Bit Mode Valid Valid Description Extract 4-bit sign mask from xmm and store in r32. Extract 4-bit sign mask from xmm and store in r64. Zero extend 32-bit results to 64-bits. Description Extracts the sign bits from the packed single-precision floating-point values in the source operand (second operand), formats them into a 4-bit mask, and stores the mask in the destination operand (first operand). The source operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored in the 4 low-order bits of the destination operand. In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the instr...
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