ia-32_instruction-set-ref_a-m

Ia-32_instruction-set-ref_a-m

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Unformatted text preview: (* Instruction = CBW *) THEN AX SignExtend(AL); ELSE IF (OperandSize = 32, Instruction = CWDE) EAX SignExtend(AX); FI; ELSE (* 64-Bit Mode, OperandSize = 64, Instruction = CDQE*) RAX SignExtend(EAX); FI; Flags Affected None. Exceptions (All Operating Modes) None. 3-104 Vol. 2 INSTRUCTION SET REFERENCE, A-M CLC--Clear Carry Flag Opcode F8 Instruction CLC 64-Bit Mode Valid Compat/ Leg Mode Valid Description Clear CF flag. Description Clears the CF flag in the EFLAGS register. Operation is the same in all non-64-bit modes and 64-bit mode. Operation CF 0; Flags Affected The CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected. Exceptions (All Operating Modes) None. Vol. 2 3-105 INSTRUCTION SET REFERENCE, A-M CLD--Clear Direction Flag Opcode FC Instruction CLD 64-Bit Mode Valid Compat/ Leg Mode Valid Description Clear DF flag. Description Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index registers (ESI and/or EDI). Operation is the same in all non-64-bit modes and 64-bit mode. Operation DF 0; Flags Affected The DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected. Exceptions (All Operating Modes) None. 3-106 Vol. 2 INSTRUCTION SET REFERENCE, A-M CLFLUSH--Flush Cache Line Opcode 0F AE /7 Instruction CLFLUSH m8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Flushes cache line containing m8. Description Invalidates the cache line that contains the linear address specified with the source operand from all levels of the processor cache hierarchy (data and instruction). The invalidation is broadcast throughout the cache coherence domain. If, at any level of the cache hierarchy, the line is inconsistent with memory (dirty) it is written to memory before invalidation. The source operand is a byte memory location. The availability of CLFLUSH is indicated by the presence of the CPUID feature flag CLFSH (bit 19 of the EDX register, see "CPUID--CPU Identification" in this chapter). The aligned cache line size affected is also indicated with the CPUID instruction (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1). The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It should be noted that processors are free to speculatively fetch and cache data from system memory regions assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh instructions can be used to provide the processor with hints for this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be speculatively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references the cache line). CLFLUSH is onl...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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