ia-32_instruction-set-ref_a-m

Movq instruction when destination operand is rm64

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Unformatted text preview: in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.SSE3(ECX, bit 0) is 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-612 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVDQA--Move Aligned Double Quadword Opcode 66 0F 6F /r 66 0F 7F /r Instruction MOVDQA xmm1, xmm2/m128 MOVDQA xmm2/m128, xmm1 64-Bit Mode Valid Valid Compat/ Leg Mode Valid Valid Description Move aligned double quadword from xmm2/m128 to xmm1. Move aligned double quadword from xmm1 to xmm2/m128. Description Moves a double quadword from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. To move a double quadword to or from unaligned memory locations, use the MOVDQU instruction. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST SRC; (* #GP if SRC or DEST unaligned memory operand *) Intel C/C++ Compiler Intrinsic Equivalent MOVDQA MOVDQA __m128i _mm_load_si128 ( __m128i *p) void _mm_store_si128 ( __m128i *p, __m128i a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #PF(fault-code) #GP(0) If a page fault occurs. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. Vol. 2 3-613 INSTRUCTION SET REFERENCE, A-M #SS(0) #NM #UD If a memory operand effective address is outside the SS segment limit. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0 Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH. #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #UD For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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