ia-32_instruction-set-ref_a-m

Machine check exception exception 18 is defined for

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Unformatted text preview: a compatible mechanism for error reporting in P6 family, Pentium 4, Intel Xeon processors, and future processors, is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported. Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory on a 4K granularity through a linear address. 36-Bit Page Size Extension. Extended 4-MByte pages that are capable of addressing physical memory beyond 4 GBytes are supported. This feature indicates that the upper four bits of the physical address of the 4-MByte page is encoded by bits 13-16 of the page directory entry. Processor Serial Number. The processor supports the 96-bit processor identification number feature and the feature is enabled. CLFLUSH Instruction. CLFLUSH Instruction is supported. Reserved Debug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities (see Chapter 18, "Debugging and Performance Monitoring," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B). Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control. Intel MMX Technology. The processor supports the Intel MMX technology. FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXRSTOR instructions. SSE. The processor supports the SSE extensions. SSE2. The processor supports the SSE2 extensions. 15 CMOV 16 PAT 17 PSE-36 18 19 20 21 PSN CLFSH Reserved DS 22 ACPI 23 24 MMX FXSR 25 26 SSE SSE2 Vol. 2 3-175 INSTRUCTION SET REFERENCE, A-M Table 3-16. More on Feature Information Returned in the EDX Register (Contd.) Bit # 27 Mnemonic SS Description Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus. Multi-Threading. The physical processor package is capable of supporting more than one logical processor. Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC). Reserved Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an in...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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